1. Field of the Invention
This invention relates to a liquid crystal display device and to a method of driving the same. More particularly, the invention relates to a liquid crystal display device which has an alignment regulating structure regulating the alignment of vertically aligned liquid crystal and to a method of driving the same.
2. Background of the Invention
A liquid crystal display device has a pair of substrates arranged facing each other, and a liquid crystal sealed between the two substrates. In the liquid crystal display device of the MVA (multi-domain vertical alignment) mode, the vertically aligned type liquid crystal having a negative dielectric anisotropy is regulated for the alignment due to the alignment regulating structure, such as protrusions partly formed on the substrate, slits in the electrode, or the like (see, for example, Japanese Patent No. 2947350). The liquid crystal display device of the MVA mode possesses such advantages as a high response time, a high contrast and a wide viewing angle as compared to the liquid crystal display devices of other display modes such as TN (twisted nematic) mode or IPS (in-plane switching) mode. Owing to improvements in the characteristics of the liquid crystal materials and drive system in the liquid crystal display devices of the TN mode and IPS mode in recent years, however, there has been realized a response of a speed higher than that of the conventional MVA mode. Further, if consideration is given to coping with the dynamic picture display such as in the use of TV receivers, the response characteristics of the liquid crystal display device of the conventional MVA mode are not necessarily satisfactory.
FIG. 11 illustrates an equivalent circuit of a pixel in a conventional general liquid crystal display device. Referring to FIG. 11, each pixel is provided with a thin-film transistor (TFT) as a switching element. The gate electrode of the TFT is connected to a gate bus line and is applied with a predetermined gate voltage Vg. The drain electrode of the TFT is connected to a drain bus line and is applied with a predetermined data voltage Vd. The source electrode of the TFT is connected to the electrodes on one side of a liquid crystal capacitance Clc and of a storage capacitor Cs. The electrodes on the other side of the liquid crystal capacitance Clc and the storage capacitor Cs are maintained at a common voltage Vcom.
FIG. 12(a) is a graph illustrating a gate voltage Vg applied to the gate bus line connected to the gate electrode of the TFT of a given pixel, FIG. 12(b) is a graph illustrating a data voltage Vd (absolute value) applied to the drain bus line connected to the drain electrode of the TFT in the pixel, and FIG. 12(c) is a graph illustrating the brightness of the pixel. The abscissas of FIGS. 12(a) to 12(c) represent the time, the ordinate of FIGS. 12(a) and 12(b) represent the voltage levels, and the ordinate of FIG. 12(c) represents the brightness (%).
Referring to FIG. 12(a), a voltage Vgon (gate pulse) is applied to the gate electrode of the TFT of the pixel at times t0, t1, t2, . . . of every frame period, and the TFT is periodically turned on. When the TFT is turned on, the data voltage Vd is applied to the pixel electrode of the pixel, and the electric charge is stored in the liquid crystal capacitance Clc and in the storage capacitor Cs. The stored electric charge is held for one frame period until the TFT is turned on next. Referring to FIG. 12(b), the data voltage Vd applied to the drain bus line is changing between a time t0 and a time t1 from a voltage Vd1 displaying back to a voltage Vd2 displaying white (|Vd2|>|Vd1|). That is, before the time t0, the voltage Vd1 is applied to the pixel electrode of the pixel and after the time t1, the voltage Vd2 is applied. Here, the frame period from the time t1 at which the voltage applied to the pixel electrode changes, is referred to as the first frame. In the first frame, the state of alignment of liquid crystal in the pixel changes depending upon the electric charge stored in the liquid crystal capacitance Clc, and the brightness changes as represented by a line b1 in FIG. 12(c).
If attention is given to a change in the brightness, it will be learned that the change in the brightness is saturated in the latter half of the first frame, and the brightness changes again in the second frame. Therefore, the response waveform of brightness changes like a step for every frame period. In the conventional liquid crystal display device, the response time is lengthened due to the occurrence of two-step (multi-step) response in which the response waveform of brightness consists of two steps (or three or more steps), making it difficult to accomplish a high-speed response. Here, when the brightness changes from 0% to 100%, the time required for the brightness to change from 10% to 90% is referred to as response time.
Described below is a cause of producing the two-step response. FIG. 13(a) is a graph illustrating a relationship between the voltage applied to the liquid crystal and the brightness, and FIG. 13(b) is a graph illustrating a relationship between the voltage applied to the liquid crystal and the liquid crystal capacitance Clc. The abscissas of FIGS. 13(a) and 13(b) represent applied voltages, the ordinate of FIG. 13(a) represents the level of brightness, and the ordinate of FIG. 13(b) represents the liquid crystal capacitance Clc. The applied voltage at a starting brightness Boff which is the black display is denoted by Voff, and the liquid crystal capacitance is denoted by Clcoff. Further, the applied voltage at a target brightness Bon which is the white display is denoted by Von. As shown in FIGS. 13(a) and 13(b), the voltage Von (arrow x1 in FIG. 13(b)) is applied to the liquid crystal at the beginning of the first frame. Then, the electric charge Q (=(Clcoff+Cs)×Von) is stored in the liquid crystal capacitance Clc and in the storage capacitor Cs, and is held for one frame period. When the liquid crystal responds upon the application of the voltage Von, the liquid crystal capacitance Clc increases by ΔClc in the first frame due to the dielectric anisotropy of the liquid crystal. On the other hand, the electric charge Q remains constant due to the law of retention of electric charge. Therefore,Q=(Clcoff+ΔClc+Cs)×(Von−ΔV)and the voltage applied to the liquid crystal decreases by ΔV in the first frame as represented by an arrow x2 along a curve q of an equal electric charge. Therefore, the brightness B1 that is reached in the first frame becomes lower than the target brightness Bon. Similarly, though the voltage Von is applied (arrow x3) at the beginning of the second frame, the applied voltage decreases (arrow x4) accompanying a change in the liquid crystal capacitance Clc, and the brightness B2 reached in the second frame becomes lower than the target brightness Bon. Therefore, several frames are necessary before the brightness of the pixel reaches the target brightness Bon. Due to a decrease in the applied voltage caused by an increase in the liquid crystal capacitance Clc, the change in the brightness is saturated in the frame period, i.e., a two-step response of brightness occurs.
To accomplish a high-speed response of the liquid crystal display device suppressing the two-step response of brightness, the following two methods were so far considered.    (1) To relatively decrease the effect of change in the liquid crystal capacitance Clc by increasing the storage capacitor Cs.    (2) To increase the applied voltage of the first frame by taking a change in the liquid crystal capacitance Clc into consideration (so-called over-drive system).
However, the above method (1) has a defect in that the brightness decreases since the aperture ratio of the pixels decreases with an increase in the storage capacitor Cs.
FIG. 14(a) is a graph illustrating a relationship between the voltage applied to the liquid crystal in the liquid crystal display device using the method (2) and the brightness, and FIG. 14(b) is a graph illustrating a relationship between the voltage applied to the liquid crystal and the liquid crystal capacitance Clc. According to the method (2) as shown in FIGS. 14(a) and 14(b), the voltage applied at the beginning of the first frame is increased by Vod (arrow x5 in FIG. 14(b)) by taking a change in the liquid crystal capacitance Clc into consideration. The electric charge Q (=(Clcoff+Cs)×(Von+Vod)) is stored in the liquid crystal capacitance Clc and in the storage capacitor Cs. Accompanying an increase in the liquid crystal capacitance Clc, the applied voltage drops by Vod in the first frame (arrow x6). Therefore, a voltage Von necessary for obtaining a target brightness Bon is applied to the liquid crystal at the end of the first frame as expressed by the following formula,Q=(Clcoff+ΔClc+Cs)×(Von+Vod−Vod)=(Clcoff+ΔClc+Cs)×Von
FIG. 15(a) is a graph illustrating a gate voltage Vg applied to the gate bus line connected to the gate electrode of the TFT of a given pixel, FIG. 15(b) is a graph illustrating a data voltage Vd applied to the drain bus line connected to the drain electrode of the TFT of the above pixel, and FIG. 15(c) is a graph illustrating the brightness of the pixel. The abscissas and ordinates of FIGS. 15(a) to 15(c) are the same as the abscissas and the ordinates of FIGS. 12(a) to 12(c). A line b1 in FIG. 15(c) represents the brightness of the pixel in the conventional liquid crystal display device like the line b1 shown in FIG. 12(c), and a line b2 represents the brightness of the pixel in the liquid crystal display device of the TN mode based on the method (2). As shown in FIGS. 15(a) to 15(c), the response waveform of the brightness of the liquid crystal display device of the TN mode based on the method (2) is not forming a step; i.e., two-step response is not occurring. In the liquid crystal display device effecting a uniform alignment control processing on the whole surface of the substrate like the TN, IPS and rubbing VA modes, the two-step response is suppressed by the method (2), and a high-speed response is realized.
A line b3 of FIG. 15(c) represents the brightness of the liquid crystal display device of the MVA mode relying upon the method (2). The liquid crystal display device of the MVA mode based on the method (2) shortens the response time to some extent but is not capable of improving the two-step response. Thus, the liquid crystal display device of the MVA mode is not capable of accomplishing a high-speed response by simply applying the conventional method (2).
In order to clarify the cause which makes it difficult to increase the response speed in the liquid crystal display device of the MVA mode, the response state of the liquid crystal was observed by using a high-speed camera. FIGS. 16A to 17H are illustrating the states of response of the liquid crystal of when a voltage for displaying white is applied to the liquid crystal of a pixel displaying black in the liquid crystal display panel of the MVA mode. The liquid crystal display panel has an alignment regulating structure extending aslant (about 45°) relative to the ends of the pixel. FIGS. 16A to 17H illustrate a state where the liquid crystal display panel is held by a pair of polarizing plates arranged in cross Nicols, and is irradiated with light from the back. In FIGS. 16A to 16H, the axes of polarization of the two polarizing plates are arranged nearly in parallel with the ends of the pixel like in a general liquid crystal display device of the MVA mode and in FIGS. 17A to 17H, the axes of polarization of the two polarizing plates are arranged nearly in parallel with the direction in which the alignment regulating structure extends so that the disturbance of the liquid crystal can be easily observed. FIGS. 16A and 17A illustrate the states 40 ms after the voltage is applied, FIGS. 16B and 17B illustrate the states after 8 ms, FIGS. 16C and 17C illustrate the states after 12 ms, and FIGS. 16D and 17D illustrate the states after 20 ms. Further, FIGS. 16E and 17E illustrate the states after 32 ms, FIGS. 16F and 17F illustrate the states after 40 ms, FIGS. 16G and 17G illustrate the states after 80 ms and FIGS. 16H and 17H illustrate the states after 300 ms. As shown in FIG. 16A to 17H, the alignment of the liquid crystal is greatly disturbed just after the application of the voltage. It is learned that to obtain a desired brightness after the disturbance of alignment has extinguished, a time of about several tens of milliseconds (equivalent to several frames) is necessary from the application of voltage. In the liquid crystal display device of the MVA mode having the alignment regulating structure as described above, the high-speed response is impaired by the two-step response and by the disturbance of alignment of the liquid crystal making it impossible to obtain favorable response characteristics.
Patent document 1: Japanese Patent No. 2947350
Patent document 2: JP-A-2000-231091
Patent document 3: JP-A-2001-117074